Current Issue : January - March Volume : 2017 Issue Number : 1 Articles : 6 Articles
This paper presents a 5V-to-3.3V linear regulator circuit, which uses 3.3V CMOS transistors to replace the 5V CMOS transistors.\nThus, the complexity of themanufacturing semiconductor process can be improved.The proposed linear regulator is implemented\nby cascode architecture, which requires three different reference voltages as the bias voltages of its circuit.Thus, the three-output\ntemperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously.\nThe three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed\ntemperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable\nfor low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses\nthe cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear\nregulator has a good performance in reference voltage to output voltage isolation.The voltage variation of the linear regulator is less\nthan 2.153% in the temperature range of âË?â??40âË?Ë?Cââ?¬â??120âË?Ë?C, and the power supply rejection ratio (PSRR) is less than âË?â??42.8 dB at 60Hz.\nThe regulator can support 0âË?¼200mA output current. The core area is less than 0.16m...
In this paper, a new approach to the sliding-mode control of single-phase inverters under\nlinear and non-linear loads is introduced. The main idea behind this approach is to utilize a non-linear,\nflexible and multi-slope function in controller structure. This non-linear function makes the controller\npossible to control the inverter by a non-linear multi-slope sliding surface. In general, this sliding\nsurface has two parts with different slopes in each part and the flexibility of the sliding surface makes\nthe multi-slope sliding-mode controller (MSSMC) possible to reduce the total harmonic distortion,\nto improve the tracking accuracy, and to prevent overshoots leading to undesirable transient-states\nin output voltage that occur when the load current sharply rises. In order to improve the tracking\naccuracy and to reduce the steady-state error, an integral term of the multi-slope function is also\nadded to the sliding surface. The improved performance of the proposed controller is confirmed\nby simulations and finally, the results of the proposed approach are compared with a conventional\nsliding-mode controller (SMC) and a synchronous reference frame PI (SRFPI) controller....
A readout integrated circuit (ROIC) using two-step fastest signal identification (FSI)\nis proposed to reduce the number of input channels of a data acquisition (DAQ) block with a\nhigh-channel reduction ratio. The two-step FSI enables the proposed ROIC to filter out useless input\nsignals that arise from scattering and electrical noise without using complex and bulky circuits.\nIn addition, an asynchronous fastest signal identifier and a self-trimmed comparator are proposed\nto identify the fastest signal without using a high-frequency clock and to reduce misidentification,\nrespectively. The channel reduction ratio of the proposed ROIC is 16:1 and can be extended to\n16 Ã?â?? N:1 using N ROICs. To verify the performance of the two-step FSI, the proposed ROIC was\nimplemented into a gamma photon detector module using a Geiger-mode avalanche photodiode\nwith a lutetium-yttrium oxyorthosilicate array. The measured minimum detectable time is 1 ns.\nThe difference of the measured energy and timing resolution between with and without the two-step\nFSI are 0.8% and 0.2 ns, respectively, which are negligibly small. These measurement results show\nthat the proposed ROIC using the two-step FSI reduces the number of input channels of the DAQ\nblock without sacrificing the performance of the positron emission tomography (PET) systems....
Compared with conventional Class-A, Class-B, and Class-AB amplifiers, Class-D amplifier, also known as switching amplifier,\nemploys pulse width modulation (PWM) technology and solid-state switching devices, capable of achieving much higher efficiency.\nHowever, PWM-based switching amplifier is usually designed for low-voltage application, offering a maximum output voltage of\nseveral hundred Volts. Therefore, a step-up transformer is indispensably adopted in PWM-based Class-D amplifier to produce high voltage\noutput. In this paper, a switching amplifier without step-up transformer is developed based on digital pulse step modulation\n(PSM) and hybrid multilevel converter. Under the control of input signal, cascaded power converters with separate DC sources\noperate in PSMs witch mode to directly generate high-voltage and high-power output.The relevant topological structure, operating\nprinciple, and design scheme are introduced. Finally, a prototype system is built, which can provide power up to 1400 Watts and\npeak voltage up to �±1700 Volts. And the performance, including efficiency, linearity, and distortion, is evaluated by experimental\ntests....
Noise parameters of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) for different sizes are investigated in\nthe breakdown region for the first time. When the emitter length of SiGe HBTs shortens, minimum noise figure at breakdown\ndecreases. In addition, narrower emitter width also decreases noise figure of SiGe HBTs in the avalanche region. Reduction of\nnoise performance for smaller emitter length and width of SiGe HBTs at breakdown resulted from the lower noise spectral density\nresulting from the breakdown mechanism. Good agreement between experimental and simulated noise performance at breakdown\nis achieved for different sized SiGe HBTs.The presented analysis can benefit the RF circuits operating in the breakdown region....
This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a\nfamily that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and\nNOR gates are investigated using the stuck at fault model for the memristors and the five-fault\nmodel for the transistors. Test escapes may take place while testing faults in the memristors.\nTherefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates.\nThe first is to apply scaled input voltages and the second is to change the switching threshold of\nthe CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration.\nIt is proven that three ordered test vectors are needed for full coverage in MRL NAND and\nNOR gates, which is different from the order required to obtain 100% coverage in the conventional\nNAND and NOR CMOS designs....
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